1. Field of the Invention
The present invention relates to use of capture compounds such as a crown ether to facilitate selected compositions and processes employed in manufacture of electronic packaging devices such as printed circuit boards, semiconductor integrated circuit systems, multichip modules, lead frames and other interconnection devices, flat panel display substrates, and the like.
2. Background
A variety of electronic packaging devices are produced through sequential chemical processing, such as substrate catalysis for subsequent metal plating; electroless and/or electrolytic plating of numerous metals such as copper, nickel, gold, etc.; photolithographic processing; etc.
For example, in the manufacture of computer printed circuit boards, copper electrical connections are provided between various board layers by plating board through holes whereby a thin conductive copper conductive is first applied, typically using electroless copper plating techniques, followed by electroplating copper from acid copper solutions.
Copper plating is also employed in circuit board manufacture to plate outer layers where final circuitry is defined. For such applications, panel plating is typically employed, where the full circuit board surface is copper plated followed by photodefining circuitry with a photoresist and then etching in a subtractive process. Alternatively an additive process can be employed, where copper circuits are produced by plating between lines defined by a resist relief image.
Plating of copper, gold and other metals is also employed in semiconductor chip manufacture. In particular, more recently, copper plating also has been employed in semiconductor chip manufacture to provide chip interconnections. Traditionally, semiconductors have been interconnected through aluminum conductors. However, industry continually demands enhanced performance, including ultra large-scale integration and faster circuits. Consequently, chip interconnects are required at dimensions of 200 nm and less. At such geometries, the resistivity of aluminum (theoretically 2.65×10−8 ohm/meter at room temperature) is considered too high to allow the electronic signal to pass at required speeds. Copper, with a theoretical resistivity of 1.678×10−8 ohm/meter, is considered a more suitable material to meet the next generation of semiconductor microchips.
Typical processes for defining semiconductor chip interconnects, particularly aluminum interconnects, have involved reactive ion etching of metal layers, e.g. a process that includes metal deposition, photolithographic patterning, line definition through reactive ion etching and dielectric deposition. In Cu-based systems, reactive ion etching is not practical, however, as a result of the paucity of copper compounds with vapor pressures sufficient to enable removal of the copper as may be desired.
Consequently, alternative strategies have developed, such as the Damascene process. That process starts with deposition of dielectric typically by chemical vapor deposition of silicon materials or organic dielectrics followed by curing, or spin coating silicon materials or organic dielectrics. Patterning by photolithographic processes and reactive ion etching defines the vias and trenches (interconnects) in the dielectric. Barrier layers are then formed by chemical vapor deposition or other methods to isolate the copper lines from the dielectric. Copper is then deposited and excess material removed by chemical or mechanical polishing processes.
Although conventional copper plating systems can be suitable for plating vias and trenches as small as 300 nm with 4:1 aspect ratios, defects such as seams, voids and inclusions can occur with conventional methods when attempting to plate features that are smaller or have higher aspect ratios. Accordingly, the need exists high performance copper and other metal plating compositions that can effectively plate (i.e. reduced or absence of such seams, voids and inclusions) such features.
It thus would be desirable to have new electroplating compositions. It would be particularly desirable to have new copper electroplating compositions that can plate effectively (e.g. absence of voids, inclusions and seams) high aspect ratio apertures, including high aspect ratio microvias as discussed above.